The present invention relates generally to detection of defects in semiconductor device processing. More specifically, the present invention relates to methods of detecting over-etch defects in devices having pn junctions.
As semiconductor devices shrink in size, new challenges present themselves. The shrinking in device sizes is often accompanied by an increase in the number of contacts and especially self-aligning contacts. The rising number of self-aligning contacts is making overall contact formation more challenging. Detecting defects such as over-etch in self-aligning contact formation is likewise increasingly challenging.
Current automated optical imaging and light-scattering inspection technologies have limited success detecting defects within high aspect ratio structures such as self-aligning contacts which are becoming more prevalent as device sizes adjacent to gates in the formation of metal oxide semiconductor field effect transistors (MOSFET or MOS).
When a contact is over-etched, the spacer adjacent to a gate is etched into and may easily cause a short or cause leakage between the source and/or the drain contact and the polysilicon or polysilicide gate. In many cases, the defect shorting the gate and the source or drain regions will escape detection by conventional inspection techniques.
However, such defects may be inspected after fabrication of the device is complete and electrically tested. For example, the source or drain and gate pads may be electrically probed for shorts. Unfortunately, waste of time and materials may be expended if detection of defects must await final device assembly. Destructive techniques are also available off-line after specific process steps but render the tested device unusable. That is, the wafer is removed from the clean room to undergo electrical probing. Once removed, the wafer cannot be reinserted into the process flow.
Therefore, what is needed is a non-destructive in-line method for detecting over-etch defects in MOS devices at an early stage of the fabrication process using inspection equipment that is available during the process flow, such as a scanning electronic beam microscope (SEM).
To achieve the foregoing, the present invention provides apparatus and methods for detecting over-etch defects associated with contacts in a semiconductor device. An over-etched defect is detected by applying an electrical field to the contacts in a candidate area and comparing the intensity measured with the intensity from a reference area. In one embodiment, one of the contacts in each of the candidate and reference areas is a gate contact in an MOS device and a second contact is either a source or drain contact. The selected electrical charging field forward biases the pn junctions between the source and drain regions and the well in which they are formed. As a result, defects caused by gate contacts shorted to one of the source and drain contacts are visible using voltage contrast imaging techniques. In other words, a defective contact has a different imaged appearance during a voltage contrast inspection than a non-defective reference contact. In one embodiment, if a minority of imaged contacts have a different appearance than a majority of imaged contacts, the minority are determined to be defective.
In one aspect, the present invention provides a method of detecting an over-etched defect. An electrical field is applied above a wafer having a candidate area and a reference area. Each of the candidate area and the reference area has a portion with a first contact connected to a pn junction and a second contact separated by a spacer from the first contact. The electrical field is selected to forward bias the pn junction. An intensity difference of detected electrons between contacts in the candidate area and the reference area is determined. In a further aspect, it is determined that a defect exists when the intensity difference exceeds a predetermined threshold.
In another aspect, the inspected portion of the wafer is a PMOS device and an extracting electrical field is applied. The first contact is either a source or drain contact and the second contact is a gate contact.
In yet another aspect of the invention, the inspected portion of the wafer is an NMOS device and a retarding electrical field is applied. The first contact is either a source or drain contact and the second contact is a gate contact.
These and other features and advantages of the present invention are described below with reference to the drawings.